Pertinent prior art systems comprise a ONE to ONE correspondence between the tested elements of the physical model and a reference model, e.g. the gates or latches. For the verification of physical failures in those systems a test unit applies to the physical model stimuli patterns and receives response patterns from this model, which are compared with simulated response patterns of a reference model, to which the same stimuli patterns were applied.
These deterministic tests are not suitable for covering the whole spectrum of operations of a physical logic unit. Therefore, in the last years pseudo-random tests have been used for test data generation purposes. Those pseudo-random tests all work in a similar way:
1. All bistable elements (called in the following SRLs for PA1 2. If all SRLs have been set up with pseudo-random values, a system clock is applied, which copies the outputs of the combinational logic into the SRLs. PA1 3. The SRL values are shifted out to a Signature Register, which generates a compressed signature of the logic values, which were generated by the combinational logic. This signature value is compared with a simulated signature. PA1 1. There is no equivalent to an architecture model since the effort required is prohibitive. PA1 2. In the test of bus protocols not only the sequence of operations is important, but in addition the starting times of the different operations and the relationship between these starting times. It is emphasized that in a processor the instruction sequence determines exactly, at which time the instruction is executed.
Shift Register Latches) are set up to pseudo-random values. The SRLs are connected into one or several shift chains and a Pseudo-Random Pattern Generator (PRPG) supplies the data at the inputs of the shift chain. During that phase the SRLs are clocked in such a way that the value of an SRL is sent to the next SRL in the shift chain. The outputs of the combinational logic are not fed into the SRLs.
Central to that well-known approach is the premise that values of all bistable elements comprising a state vector could be controlled and observed.
In the area of the verification of design errors, deterministic tests are also not sufficient. These tests are difficult to generate and their test coverage is often quite low. Therefore, random tests have been used for several years to verify e.g. a processor implementation against the underlying processor architecture. In that case, random instruction streams are generated, and at the end of an instruction stream the value of the architected state vector, e.g. registers, condition codes or memory contents, is compared with a simulated value. The simulated value is derived from a high level description of the architecture, i.e. the architecture model, which abstracts implementation details, e.g. the number of pipeline stages or the number of instruction units. It is obvious that the architecture state vector is a subset of the implementation state vector and that there is no ONE to ONE correspondence between the architecture and the implementation. Due to this, much effort is required to describe the architecture model. This effort is only justified for processor architectures, which typically last much longer than processor implementations.
Further, the approach described above is not very useful for testing bus protocols or data communication protocols for two reasons:
Since there is no equivalent to an architecture model the compare values must be predicted. In particular, the prediction of the total state vector of a system is very error prone and time consuming.
U.S. Pat. No. 4,688,222 discloses a method for error testing and diagnosing processors which includes technology and design relevant errors and wherein pseudo-random generated test programs or pseudo-random operation codes are employed which have been previously stored in a test program memory. This method applies random test patterns to the processor under test in a predefined time sequence, and is directed to the verification of physical failures, but not design relevant logic failures. It is based on changes of the total system state, wherein only this system state is detected.
The above-mentioned approaches according to the state of the art all have the disadvantage that they only check physical failures in logic devices. Those test units use correct reference models which can exist as a physical reference model or a mathematical abstraction of such a unit. This reference model is considered as working correctly in the system environment. Verification is fulfilled by comparing the physical copies with the reference model.